ExpectedOutcome:
Proposal results are expected to contribute to:
- Multiple levels of the computer design hierarchy, ranging from (semiconductor) technologies for low power, secure, or high-performance hardware realisations, through hardware organisations (microarchitectures), up to customised RISC-V Instruction Set Architectures. The expected results must have the potential for quick commercialisation after the end of the project, in order to demonstrate industrial relevance, feasibility and possible business models. The expected results must be aligned with demands and conform with user requirements. The IP- and functional blocks must be validated for industrial use, in order to create low-threshold access to RISC-V.
- System software and support by appropriate design approaches and toolchains.
- Development of industrial qualified open-source building blocks should be in line with the roadmaps developed under HORIZON-CL4-2021-DIGITAL-EMERGING-01-05: Open Source Hardware for ultra-low-power, secure processors
Proposals should also lay the groundwork for future exploitation and further enhancements. If successful, those could be supported by future calls within KDT and/or other programs. Ultimately, the efforts should accelerate the developments in the field of open-source hardware and render it accessible to a wider community.
Special attention should be paid to the inclusion of industrial players and a user centric view in the consortia.
Scope:
Proposals for this call will develop RISC-V compliant IP blocks. Certain IP blocks may be proprietary solutions; however, a large share of developed building blocks provided with a permissive open-source licence is preferred. All developed blocks must come with publicly available documentation, benchmarks, verification suites, and validated reference designs (including firmware/drivers, if required).
For this call, the RISC-V architectural aspect of the proposed IP building blocks should be clearly identifiable. Furthermore, each IP block should be able to demonstrate the optimisation goals it was designed for (low power, high security, processing acceleration, etc.) in realistic application contexts and appropriate use cases.
The following is a list of building blocks of which some must be developed in the proposed project. This list is not definitive but rather an indication of the kind of blocks. A definitive list should be discussed with the consortia selected under HORIZON-CL4-2021-
DIGITAL-EMERGING-01-05. In addition, the selected building blocks must support the common European roadmap and the ecosystem for RISC-V.
- Extend the RISC-V core IP towards a scalable and fit-for-purpose architecture ranging between MCU-like (lower end) and microprocessors/network processors-like (higher end).
- High-speed memory interfaces for advanced DDR (at least DDR3+ SDRAM) controllers, high-speed peripheral interfaces like scalable advanced PCI (at least PCIe Gen3+) interfaces, including the required SerDes PHYs.
- Support for heterogeneous many-core SoCs, specifically scalable coherent cache infrastructure, scratchpad memory infrastructure with smart DMA, and a flexible NoC to connect cores (including accelerators)/memory/IO while considering caching/coherency.
- Inter-chip communication links (e.g., for interfacing with FPGAs or other ASICs) with at least 2 Gb/s per pin.
- Support for extended virtualization mechanisms and hardware multitasking, in particular in the area of cache management and interrupt controllers (PLIC, CLINT);
- A minimum set of test, trace and debug IPs (JTAG controllers, …).
- System and SoC simulation as well as validation environments and tools to allow for very early SW migration and respective performance assessments. Accelerating the design and validation process to shorten time-to-market for new architectures and system concepts.
In addition to the RISC-V blocks listed above, the following technologies are considered as examples of useful complements to the base blocks, and are considered in scope for this call if developed in open-source form, again with documentation, verification and validation suites:
- Holistic architectural approaches for HW/SW co-design of computing systems (compilers, design tools, architectural extensions or microarchitectures targeting various semiconductor technologies) under open-source licenses.
- Chiplet, interposer and especially high-bandwidth, low-latency, low-energy die-to-die communication technologies.
- Template PCB designs for PCIe-attached accelerators, similar to existing FPGA evaluation/prototyping boards, but allowing the easy integration of a user-provided ASIC instead of an FPGA,
- Communication peripheral interfaces, specifically Ethernet (at least 1G) and USB (at least 2.0).
According to the strategy defined in the projects of HORIZON-CL4-2021-DIGITAL-EMERGING-01-05 and the common European roadmap for RISC-V, proposals will also need to develop re-usable verification infrastructure that supports a repository, which includes IP blocks accompanied by test frameworks for safety/security.
A compliance standard is defined that certifies interoperability and industrial readiness of open-source hardware solutions. For the application in safety-critical environments, this compliance standard should include the requirements in accordance with relevant safety standards, e.g. ISO 26262. If other standards are relevant, they should be considered in the proposal too.
One or more demonstrators should be built in a close to industrial environment with a number of RISC-V building blocks in combination with necessary proprietary IP relevant for the application areas of interest. For instance, in the safety/security area, hardware/software co-certification for safety and security should be demonstrated.
A software development platform must be created (for compiler, linker, debugger, middleware, etc.) that proposes highly efficient code (in terms of power, speed, etc.) based on state-of-the-art programming languages.
Some of the developed building blocks could be supported by the current EUROPRACTICE- processes at 65 nm and smaller.
In terms of exploitation, the proposals must assess the sustainable provisions to support industrial use, including administrative and legal support, especially towards SMEs. The developed methods and standards should be prepared for incorporation into an organisation/setup that makes the results industrially available beyond project duration.
Of importance to this call are:
- All proposals are encouraged to allocate tasks to cohesion activities with relevant actions funded nationally, under EuroHPC (including the European Processor Initiative), or any other actions on RISC-V.
- All proposals are encouraged to allocate tasks to cohesion activities with the projects selected under the call HORIZON-CL4-2021-DIGITAL-EMERGING-01-05: Open Source Hardware for ultra-low-power, secure processors (CSA) and to support and lay the groundwork for the further development of the common European roadmap for RISC-V.
- Where relevant, synergies with other European partnerships and any of the Horizon Europe Clusters are encouraged. . Proposals must describe how the consortia ensure complementarity to other funded actions.
Reminding that of general importance to the KDT calls are:
- Re-use of results from previous ECSEL JU, H2020 or EUREKA-cluster projects is encouraged.
- Developing synergies with other relevant European, national or regional initiatives and/or funding programmes.
- Encouraging SMEs to participate in those developments, in particular paying attention to the needs of SMEs, involve SMEs in project execution, and develop solutions that can be taken up and/or exploited by SMEs
